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xicor, inc. 1994, 1995, 1996 patents pending 7052 10/29/00 t0/c0/d2 sh 1 characteristics subject to change without notice 128k x76f128 16kx8+64x8 functional diagram secure features ? 64-bit password security five 64-bit passwords for read, program and reset ? 16384 byte+64 byte password protected arrays seperate read passwords seperate write passwords reset password ? programmable passwords ? retry counter register allows 8 tries before clearing of both arrays password protected reset ? 32-bit response to reset (rst input) ? 64 byte sector program ? 400khz clock rate ? 2 wire serial interface ? low power cmos 2.7 to 5.5v operation standby current less than 1a active current less than 3 ma ? high reliability endurance: 100,000 write cycles ? data retention: 100 years ? available in: smartcard module tqfp package description the x76f128 is a password access security supervisor, containing one 131072-bit secure serialflash array and one 512-bit secure serialflash array. access to each memory array is controlled by two 64-bit passwords. these passwords protect read and write operations of the memory array. a separate reset password is used to reset the passwords and clear the memory arrays in the event the read and write passwords are lost. the x76f128 features a serial interface and software protocol allowing operation on a popular two wire bus. the bus signals are a clock input (scl) and a bidirec- tional data input and output (sda). access to the device is controlled through a chip select (cs ) input, allowing any number of devices to share the same bus. the x76f128 also features a synchronous response to reset providing an automatic output of a hard-wired 32-bit data stream conforming to the industry standard for memory cards. the x76f128 utilizes xicors proprietary direct write tm cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. logic cs scl sda rst interface 16k byte data transfer array access enable reset response register password array and password verification logic chip enable retry counter serialflash array 64 byte serialflash array array 0 array 1 (password protected) (password protected) 7052 fm 01
x76f128 2 pin descriptions serial clock (scl) the scl input is used to cloc k all data into and out of the de vice . serial data (sda) sd a is a tr ue three state ser ial data input/output pin. dur- ing a read cycle , data is shifted out on this pin. dur ing a wr ite cycle , data is shifted in on this pin. in all other cases , this pin is in a high impedance state . chip enable ( cs ) when cs is high, the x76f128 is deselected and the sd a pin is at high impedance and unless an inter nal wr ite oper ation is underw a y , the x76f128 will be in standb y mode . cs lo w enab les the x76f128, placing it in the activ e mode . reset (rst) rst is a de vice reset pin. when rst is pulsed high while cs is lo w the x76f128 will output 32 bits of ? x ed data which conf or ms to the standard f or synchronous response to reset. cs m ust remain lo w and the par t m ust not be in a wr ite cycle f or the response to reset to occur . see figure 11. if at an y time dur ing the response to reset cs goes high, the response to reset will be abor ted and the par t will retur n to the standb y state . the response to reset is "mask prog r ammab le" only! device operation there are tw o pr imar y modes of oper ation f or the x76f128; protected read and protected write. protected oper ations m ust be perf or med with one of f our 8-b yte pass w ords . the basic method of comm unication f or the de vice is estab lished b y ? rst enab ling the de vice ( cs lo w), gen- er ating a star t condition, then tr ansmitting a command, f ollo w ed b y the correct pass w ord. all par ts will be shipped from the f actor y with all pass w ords equal to 0. the user m ust perf or m a ck p olling to deter mine the v alidity of the pass w ord, bef ore star ting a data tr ansf er (see ac kno wledge p olling.) only after the correct pass- w ord is accepted and a a ck polling has been perf or med, can the data tr ansf er occur . t o ensure the correct comm unication, rst m ust remain lo w under all conditions e xcept when r unning a response to reset sequence. data is tr ansf erred in 8-bit segments , with each tr ansf er being f ollo w ed b y an a ck, gener ated b y the receiving de vice . if the x76f128 is in a non v olatile wr ite cycle a no a ck (sd a=high) response will be issued in response to load- ing of the command b yte . if a stop is issued pr ior to the non v olatile wr ite cycle the wr ite oper ation will be ter mi- nated and the par t will reset and enter into a standb y mode . the basic sequence is illustr ated in figure 1. pin names pin configuration after each tr ansaction is completed, the x76f128 will reset and enter into a standb y mode . this will also be the response if an unsuccessful attempt is made to access a protected arr a y . symbol description cs chip select input sda serial data input/output scl serial clock input rst reset input vcc supply voltage vss ground nc no connect v cc rst scl nc sda smart card cs nc 7052 fm 02 gnd 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 nc nc nc nc nc nc nc nc nc nc nc nc vcc nc nc nc nc nc nc nc nc nc rst scl vss nc nc nc nc nc nc nc nc nc cs sd a nc nc nc nc nc nc nc nc nc nc nc nc 7052 fm t01
x76f128 3 figure 1. x76f128 device operation retry counter the x76f128 contains a retr y counter . the retr y counter allo ws 8 accesses with an in v alid pass w ord bef ore an y action is tak en. the counter will increment with an y com- bination of incorrect pass w ords . if the retr y counter o v er- ? o ws , all memor y areas are cleared and the de vice is loc k ed b y pre v enting an y read or wr ite arr a y pass w ord matches . the pass w ords are unaff ected. if a correct pass w ord is receiv ed pr ior to retr y counter o v er? o w , the retr y counter is reset and access is g r anted. in order to reset the oper ation of a loc k ed up de vice , a special reset command m ust be used with a reset p assw ord . device protocol the x76f128 suppor ts a bidirectional b us or iented pro- tocol. the protocol de? nes an y de vice that sends data onto the b us as a tr ansmitter and the receiving de vice as a receiv er . the de vice controlling the tr ansf er is a master and the de vice being controlled is the sla v e . the master will alw a ys initiate data tr ansf ers and pro vide the cloc k f or both tr ansmit and receiv e oper ations . theref ore , the x76f128 will be considered a sla v e in all applications . clock and data conventions data states on the sd a line can change only dur ing scl lo w . sd a changes dur ing scl high are reser v ed f or indicating star t and stop conditions . ref er to figure 2 and figure 3. start condition all commands are preceeded b y the star t condition, which is a high to lo w tr ansition of sd a when scl is high. the x76f128 contin uously monitors the sd a and scl lines f or the star t condition and will not respond to an y command until this condition is met. a star t ma y be issued to ter minate the input of a control b yte or the input data to be wr itten. this will reset the de vice and lea v e it ready to begin a ne w read or wr ite command. because of the push/pull output, a star t can- not be gener ated while the par t is outputting data. star ts are inhibited while a wr ite is in prog ress . stop condition all comm unications m ust be ter minated b y a stop condi- tion. the stop condition is a lo w to high tr ansition of sd a when scl is high. the stop condition is also used to reset the de vice dur ing a command or data input sequence and will lea v e the de vice in the standb y po w er mode . as with star ts , stops are inhibited when outputting data and while a wr ite is in prog ress . acknowledge ac kno wledge is a softw are con v ention used to indicate successful data tr ansf er . the tr ansmitting de vice , either master or sla v e , will release the b us after tr ansmitting eight bits . dur ing the ninth cloc k cycle the receiv er will pull the sd a line lo w to ac kno wledge that it receiv ed the eight bits of data. the x76f128 will respond with an ac kno wledge after recognition of a star t condition and its sla v e address . if both the de vice and a wr ite condition ha v e been selected, the x76f128 will respond with an ac kno wledge after the receipt of each subsequent eight-bit w ord. reset device command the reset device command is used to clear the retr y counter and reactiv ate the de vice . when the reset device command is used pr ior to the retr y counter o v er? o w , the retr y counter is reset and no arr a ys or pass- w ords are aff ected. if the retr y counter has o v er? o w ed, all memor y areas are cleared and all commands are b loc k ed and the retr y counter is disab led. issuing a v alid reset device command (with reset pass w ord) to the de vice resets and re-enab les the retr y counter and re- enab les the other commands . again, the pass w ords are not aff ected. reset password command a reset p assw ord command will clear both arr a ys and set all pass w ords to all z ero . lo ad command byte lo ad 2 byte address lo ad 8-byte p assw ord verify p assw ord a ccept ance by use of p assw ord a ck polling read/write d a t a bytes 7052 fm 03 t wc or d a t a a ck polling
x76f128 4 figure 2. data validity figure 3. definition of start and stop conditions table 1. x76f128 instruction set notes: illegal command codes will be disregarded. the par t will respond with a no-a ck to the illegal b yte and then retur n to the standb y mode . all wr ite/read oper ations require a pass w ord. 1st byte after start 1st byte after password 2nd byte after password command description password used 1000 0000 high address low address read (array 0) read 0 1000 1000 high address low address read (array 1) read 1 1001 0000 high address low address sector write (array 0) write 0 1001 1000 high address low address sector write (array 1) write 1 1010 0000 0000 0000 0000 0000 change read 0 password read 0 1010 1000 0000 0000 0000 0000 change read 1 password read 1 1011 0000 0000 0000 0000 0000 change write 0 password write 0 1011 1000 0000 0000 0000 0000 change write 1 password write 1 1100 0000 0000 0000 0000 0000 change reset password reset 1110 0000 not used not used reset password command reset 1110 1000 not used not used reset device command reset 1111 0000 not used not used ack polling command (ends password operation) none all the rest reserved scl sd a data stab le data change 7052 fm 04 scl sd a star t condition stop condition 7052 fm 05 7052 fm t04
x76f128 5 program operations sector programming the sector prog r am mode requires issuing the 8-bit wr ite command f ollo w ed b y the pass w ord, pass w ord ac k com- mand, the address and then the data b ytes tr ansf erred as illustr ated in ? gure 4. up to 64 b ytes ma y be tr ans- f erred. after the last b yte to be tr ansf erred is ac kno wl- edged a stop condition is issued which star ts the non v olatile wr ite cycle . figure 4. sector programming data 63 a ck a ck s st ar t command a ck a ck a ck a ck a ck a ck a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 wr ite p ass w ord 7 wr ite p ass w ord 0 a ck data 0 s sd a w ait t wc data a ck p olling . . . w ait t wc or st op ack polling a ck s a ck p olling repeated command command na ck if a ck, then p ass w ord matches 7052 fm 07 st ar t
x76f128 6 ack polling once a stop condition is issued to indicate the end of the host s wr ite sequence , the x76f128 initiates the inter nal non v olatile wr ite cycle . in order to tak e adv antage of the typical 5ms wr ite cycle , a ck polling can begin immediately . this in v olv es issuing the star t condition f ollo w ed b y the ne w command code of 8 bits (1st b yte of the protocol.) if the x76f128 is still b usy with the non v olatile wr ite oper ation, it will issue a no-a ck in response . if the non v olatile wr ite oper ation has completed, an a ck will be retur ned and the host can then proceed with the rest of the protocol. after the pass w ord sequence , there is alw a ys a non v ola- tile wr ite cycle . this is done to discour age r andom guesses of the pass w ord if the de vice is being tampered with. in order to contin ue the tr ansaction, the x76f128 requires the master to perf or m an a ck polling with the speci? c code of f0h. as with regular ac kno wledge polling the user can either time out f or 10ms , and then issue the a ck polling once , or contin uously loop as descr ibed in the ? o w . if the pass w ord that w as inser ted w as correct, then an a ck will be retur ned once the non v olatile cycle is o v er , in response to the a ck polling cycle immediately f ollo wing it. if the pass w ord that w as inser ted w as incorrect, then a no a ck will be retur ned e v en if the non v olatile cycle is o v er . theref ore , the user cannot be cer tain that the pass w ord is incorrect until the 10ms wr ite cycle time has elapsed. data a ck p olling sequence a ck retur ned ? issue ne w command code wr ite sequence completed enter a ck p olling issue st ar t no yes pr oceed 7052 fm 08 p ass w or d a ck p olling sequence a ck retur ned ? issue p ass w ord a ck command p ass w ord load completed enter a ck p olling issue st ar t no yes pr oceed 7052 fm 09 figure 5. acknowledge polling 8th clk. of 8th pwd. b yte a ck clk 8th clk a ck clk a ck st ar t condition 8th bit a ck or no a ck scl sd a 7052 fm 10
x76f128 7 read operations read oper ations are initiated in the same manner as wr ite oper ations b ut with a diff erent command code . random read the master issues the star t condition and a read instr uc- tion and pass w ord, perf or ms a p ass w ord ac k p olling, then issues the w ord address . once the pass w ord has been ac kno wledged and ? rst b yte has been read, another star t can be issued f ollo w ed b y a ne w 8-bit address . random reads are allo w ed, b ut only the lo w order 8 bits can change . this limits r andom reads to a 512 b yte b loc k. theref ore , with a single pass w ord cycle only a 512 b yte b loc k of arr a y 0 ma y be accessed r andomly . t o r andomly access another b loc k of arr a y 0, a stop m ust be issued f ol- lo w ed b y a ne w command/address/pass w ord sequence . a r andom read of the arr a y 1 can access all locations with- out another pass w ord command sequence . sequential read the host can read sequentially within an arr a y after the pass w ord acceptance sequence . the data output is sequential, with the data from address n f ollo w ed b y the data from n+1. the address counter f or read oper ations increments all address bits , allo wing the entire memor y arr a y contents to be ser ially read dur ing one oper ation. at the end of the address space (address 3fffh f or arr a y 0, 3fh f or arr a y 1), the counter rolls o v er to address 0 and the x76f128 contin ues to output data f or each ac kno wl- edge receiv ed. ref er to ? gure 7 f or the address , ac kno wl- edge and data tr ansf er sequence . an ac kno wledge m ust f ollo w each 8-bit data tr ansf er . after the last bit has been read, a stop condition is gener ated without a preceding ac kno wledge . figure 6. random read s a ck st op a7 a6 a5 a4 a3 a2 a1 a0 data y s st ar t st ar t command a ck a ck a ck a ck read p ass w ord 7 read p ass w ord 0 s sd a a ck a ck a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 data x w ait t wc or st ar t ack polling a ck s a ck p olling repeated command command na ck if a ck, then p ass w ord matches 7052 fm 11 figure 7. sequential read data x a ck s st ar t command a ck a ck a ck a ck read p ass w ord 7 read p ass w ord 0 s sd a a ck a ck a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a ck data 0 if a ck, then w ait t wc or st ar t ack polling a ck s a ck p olling repeated command command na ck p ass w ord matches st op 7052 fm 12
x76f128 8 passwords the sequence in figure 8 sho ws ho w to change (pro- g r am) the pass w ords . the prog r amming of pass w ords is done twice pr ior to the non v olatile wr ite cycle in order to v er ify that the ne w pass w ord is consistent. after the eight b ytes are entered in the second pass , a compar ison tak es place . a mismatch will cause the par t to reset and enter into the standb y mode . data a ck polling can be used to deter mine if a pass w ord has been loaded correctly , ho w e v er the data a ck com- mand m ust be issued less than 2ms after the stop bit. after this time , it cannot be deter mined if the pass w ord has been loaded correctly , without tr ying the ne w pass- w ord. t o deter mine if the ne w pass w ord has been loaded correctly the data a ck polling command is issued imme- diately f ollo wing the stop bit. if it retur ns an a ck, then the tw o passes of the ne w pass w ord entr y do not match. if it retur ns a "no a ck" then the pass w ords match and a high v oltage cycle is in prog ress . the high v oltage cycle is complete when a subsequent data a ck command retur ns an "a ck". there is no wa y to read an y of the pass w or ds. figure 8. change passwords figure 9. reset password st ar t command a ck a ck a ck a ck old p ass w ord 7 old p ass w ord 0 s sd a a ck a ck a ck ne w p ass w ord 7 p ass w ord 0 a ck a ck a ck ne w p ass w ord 7 ne w p ass w ord 0 a ck s st op if a ck, then a ck t w o b ytes of 0 w ait t wc or st ar t ack polling a ck s a ck p olling repeated command command na ck p ass w ord matches if immediate a ck, then ne w p ass w ord error data a ck p olling if immediate na ck, then ne w p ass w ord ok f ollo w ed b y a ck after ~5ms 7052 fm 13 st ar t reset p ass w ord a ck a ck a ck a ck reset p ass w ord 7 reset p ass w ord 0 s sd a w ait t wc or st ar t ack polling a ck s a ck p olling repeated command command na ck st op s if a ck, then de vice reset command 7052 fm 14
x76f128 9 figure 10. reset device st ar t reset de vice a ck a ck a ck a ck reset p ass w ord 7 reset p ass w ord 0 s sd a w ait t wc or st ar t ack polling a ck s a ck p olling repeated command command na ck st op s if a ck, then de vice reset command 7052 fm 15 absolute maximum ratings* t emper ature under bias ...................... C65c to +135c stor age t emper ature ........................... C65c to +150c v oltage on an y pin with respect to v ss ...................................... C1v to +7v d .c . output current .................................................. 5ma lead t emper ature (solder ing, 10 seconds) ................................. 300c *comment stresses abo v e those listed under absolute maxim um ratings ma y cause per manent damage to the de vice . this is a stress r ating only and the functional oper ation of the de vice at these or an y other conditions abo v e those listed in the oper ational sections of this speci? cation is not implied. exposure to absolute maxim um r ating condi- tions f or e xtended per iods ma y aff ect de vice reliability . figure 11. response to reset (rst) cs sck so 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 1 rst 7025 fm 16 lsb msb lsb msb lsb msb lsb msb byte 0 1 2 3 response to reset (default =19 28 aa 55) the iso response to reset is controlled b y the rst , cs and clk pins . when rst is pulsed high, while cs is lo w , the de vice will output 32 bits of data, one bit per cloc k. this conf or ms to the iso standard f or "synchronous response to reset". cs m ust remain lo w and the par t m ust not be in a wr ite cycle f or the response to reset to occur . after initiating a non v olatile wr ite cycle is complete . if not, the iso response will not be activ ated. also , an y attempt to pulse the rst pin in the middle of an iso tr ansaction will stop the tr ansaction with the sd a pin in high imped- ance . the user will ha v e to issue a stop condition and star t the tr ansaction again. if at an y time dur ing the response to reset cs goes hgih, the response to reset will be abor ted and the par t will retur n to the standb y state . a response to reset is not a v ailab le dur- ing a non v olatile wr ite cycle . contin ued cloc ks after the 32 bits , will output the 32 bit sequence again, star ting at b yte 0.
x76f128 10 recommended operating conditions 7052 fm t05 7052 fm t06 temp min. max. commercial 0c +70c extended C20c +85c supply voltage limits x76f128 4.5v to 5.5v x76f128 C 2.7 2.7v to 3.6v d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) 7052 fm t07 capacitance t a = +25c, f = 1mhz, v cc = 5v 7052 fm t08 no tes: (1) must perf or m a stop command after a read command pr ior to measurement (2) v il min. and v ih max. are f or ref erence only and are not tested. (3) this par ameter is per iodically sampled and not 100% tested. symbol parameter limits units test conditions min. max. i cc1 v cc supply current (read) 1 ma f scl = v cc x 0.1/v cc x 0.9 levels @ 400 khz, sda = open rst = cs = v ss i cc2 (3) v cc supply current (write) 3 ma f scl = v cc x 0.1/v cc x 0.9 levels @ 400 khz, sda = open rst = cs = v ss i sb1 (1) v cc supply current (standby) 50 a v il = v cc x 0.1, v ih = v cc x 0.9 f scl = 400 khz, f sda = 400 khz i sb2 (1) v cc supply current (standby) 1 a v sda = v s cc = v cc other = gnd or v cc C0.3v i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc v il1 (2) input low voltage C0.5 v cc x 0.3 v v cc = 5.5v v ih1 (2) input high voltage v cc x 0.7 v cc + 0.5 v v cc = 5.5v v il2 (2) input low voltage C0.5 v cc x 0.1 v v cc = 3.0v v ih2 (2) input high voltage v cc x 0.9 v cc + 0.5 v v cc = 3.0v v ol output low voltage 0.4 v i ol = 3ma symbol test max. units conditions c out (3) output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (rst, scl, cs ) 6 pf v in = 0v equivalent a.c. load circuit a.c. test conditions 7052 fm t09 3v 1.3k w output 100pf 5v 1533 w output 100pf 7052 fm 17 input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 output load 100pf
x76f128 11 ac characteristics ac specifications (over the recommended operating conditions) notes: 1. t ypical v alues are f or t a = 25?c and v cc = 5.0v notes: 2. c b = t otal capacitance of one b us line in pf . symbol parameter min typ (1) max units f scl scl clock frequency, x76f128 0 400 khz f scl sch clock frequency, x76f128C2.7 0 250 khz t in (1) pulse width of spikes which must be suppressed by the input filter 50 100 ns t aa scl low to sda data out valid 0.1 0.3 0.9 m s t buf time the bus must be free before a new transmit can start 1.3 m s t low clock low time 1.3 m s t high clock high time 0.6 m s t su:sta start condition setup time 0.6 m s t hd:sta start condition hold time 0.6 m s t su:dat data in setup time 100 ns t hd:dat data in hold time 0 m s t su:sto stop condition setup time 0.6 m s t dh data output hold time 50 300 ns t r sda and scl rise time 20 + 0.1 x c b (2) 300 ns t f sda and scl fall time 20 + 0.1 x c b (2) 300 ns t su:cs cs setup time 200 ns t hd:cs cs hold time 100 ns f scl_rst scl clock frequency during response to reset 400 khz t sr device select to rst active 200 ns t nol rst to scl non-overlap 500 ns t rst rst high time 2.25 m s t su:rst response to reset setup time 1.25 m s t low_rst clock low during response to reset 1.25 m s t high_rst clock high during response to reset 1.25 m s t rdv rst low to sda valid during response to reset 0 500 ns t cdv clk low to sda valid during response to reset 0 500 ns t dhz device deselect to sda high impedance 0 500 ns 7052 fm t14
x76f128 12 reset ac specifications power up timing notes: 1. dela ys are measured from the time v cc is stab le until the speci? ed oper ation can be initiated. these par ameters are per iodically sampled and not 100% tested. 2. t ypical v alues are f or t a = 25?c and v cc = 5.0v nonvolatile write cycle timing notes: 1. t wc is the time from a v alid stop condition at the end of a wr ite sequence to the end of the self-timed inter nal non v olatile wr ite cycle . it is the minim um cycle time to be allo w ed f or an y non v olatile wr ite b y the user , unless ac kno wledge p olling is used. timing diagrams bus timing write cycle timing symbol parameter min. typ (2) max. units t pur (1) time from power up to read 1 ms t puw (1) time from power up to write 5 ms symbol parameter min. typ.(1) max. units t wc (1) write cycle time 5 10 ms t su:st o t dh t high t su:st a t hd:st a t hd:d a t t su:d a t scl sd a in sd a out t f t lo w t b uf t aa t r 7052 fm 18 scl sd a t wc 8th bit of last b yte a ck stop condition star t condition 7052 fm 19 7052 fm t11 7052 fm t12
x76f128 13 cs timing diagram (selecting/deselecting the part) rst timing diagram C response to a synchronous reset guidelines for calculating typical values of bus pull up resistors t su:cs t hd:cs scl cs from master 7052 fm 20 t rst t nol t high_rst t lo w_rst t cd v t rd v t su:rst d a t a bit (1) d a t a bit (2) 1st clk pulse 2nd clk pulse 3rd clk pulse cs i/o clk rst t nol t sr d a t a bit (n) d a t a bit (n+1) cs i/o clk rst t dhz (n+2) 7052 fm 21 100 80 60 40 20 bus capacitance in pf pull up resistance in k w r min r max 20 40 60 80 100 r min v ccmax i olmin - - - - - - - - - - - - - - - - - - - - - - - - - -1 .8 k w == r max t r c bus - - - - - - - - - - - - - - - - - - = t r = maxim um allo w ab le sd a r ise time 7052 fm 22
x76f128 14 packaging information a2 a1 l l1 ga ge plane 0.25 c 7 0 7052 fm 23 he d e b hd e no tes: 1. gage plane dimension is in mm. 2. lead coplanarity shall be 0.10mm [0.004] maximum. 48-lead thin quad flat pack (tqfp) package type l pin 1 dim inches millimeters min max min max a 1 a 2 b c d e e hd he l l 1 0.05 1.35 0.17 0.090 7.0 bsc 9.0 bsc 0.45 0.15 1.45 0.27 0.200 0.75 0.002 0.53 0.007 0.004 0.018 0.006 0.057 0.011 0.008 0.030 1.00 typ 0.039 typ 0.5 bsc 0.02 bsc 3. mold flash not included in dimensions 9.0 bsc 0.35 bsc 0.35 bsc 7.0 bsc 0.273 bsc 0.273 bsc
x76f128 15 8 pad chip on board smart card module type x 0.465 0.002 (1 1.81 0.05) a section a-a a r. 0.078 (2.00) 0.285 (7.24) max. see note 7 sht . 2 0.420 0.002 (10.67 0.05) 0.210 0.002 (5.33 0.05) 0.105 0.002 (2.67 0.05) typ . (8x) (8x) 0.105 0.002 (2.67 0.05) 0.008 0.001 (0.20 0.03) 0.233 0.002 (5.92 0.05) 0.174 0.002 (4.42 0.05) 0.146 0.002 (3.71 0.05) die 0.0235 (0.60) max. 0.015 (0.38) max. 0.008 (0.20) max. glob size fr4 t ape see det ail sheet 3 copper, nickel pla ted, gold flash r. 0.013 (0.33) (8x) 0.270 (6.86) max. see note 7 sht . 2 0.069 (1.75) min epoxy free area (typ .) 0.088 (2.24) min epoxy free area (typ .) note: 1. all dimensions in inches and (millimeters) sc t ype x ill 1.0 vcc rst scl nc vss cs sda nc
x76f128 16 ordering information v cc limits blank = 5v 10% 2.7 = 2.7v to 3.6v temperature range blank = commercial = 0c to +70c e = extended = C20c to +85c package l = 48-lead tqfp h = die in waffle packs w = die in wafer form x = smart card module device x76f128 x x Cx limited w arranty de vices sold b y xicor , inc. are co v ered b y the w arr anty and patent indemni? cation pro visions appear ing in its t er ms of sale only . xicor , inc. mak es no w arr anty , e xpress , statutor y , implied, or b y descr iption regarding the inf or mation set f or th herein or regarding the freedom of the descr ibed de vices from patent infr ingement. xicor , inc. mak es no w arr anty of merchantability or ? tness f or an y pur pose . xicor , inc. reser v es the r ight to discontin ue production and change speci? cations and pr ices at an y time and without notice . xicor , inc. assumes no responsibility f or the use of an y circuitr y other than circuitr y embodied in a xicor , inc. product. no other circuits , patents , licenses are implied. u .s. p a tents xicor products are co v ered b y one or more of the f ollo wing u .s . p atents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. f oreign patents and additional patents pending. life rela ted policy in situations where semiconductor component f ailure ma y endanger lif e , system designers using this product should design the system with appropr iate error detec- tion and correction, redundancy and bac k-up f eatures to pre v ent such an occurence . xicor s products are not author iz ed f or use in cr itical components in lif e suppor t de vices or systems . 1. lif e suppor t de vices or systems are de vices or systems which, (a) are intended f or surgical implant into the body , or (b) suppor t or sustain lif e , and whose f ailure to perf or m, when proper ly used in accordance with instr uctions f or use pro vided in the labeling, can be reasonab ly e xpected to result in a signi? cant injur y to the user . 2. a cr itical component is an y component of a lif e suppor t de vice or system whose f ailure to perf or m can be reasonab ly e xpected to cause the f ailure of the lif e sup- por t de vice or system, or to aff ect its saf ety or eff ectiv eness .

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